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SOC RTL Integration Engineer/Lead

Santa Clara, CA — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a SOC RTL Integration Engineer/Lead. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a SOC RTL Integration Engineer/Lead, you will work with chip architects to conceive of the micro-architecture, lead the project through implementation, and also help with architecture/product definition through early involvement in the product life-cycle.

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Minimum qualifications

  • BA/BS degree in Electrical Engineering with 5+ years of practical experience
  • Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
  • Experience with ASIC design/micro-architecture, synthesis, timing/power analysis
  • Strong understanding of SoC integration challenges at subsystem and full chip level

Preferred qualifications

  • MS degree in Electrical Engineering; 10 years of practical experience
  • Delivered RTL subsystems and/or top level SoC RTL for multiple projects
  • Expertise in front end design methodologies for RTL database management, RTL partitioning, third party IP integration, lint, DFT,  UPF, and synthesis
  • Expertise in clock/reset design and voltage/power domain design 
  • Domain knowledge in one or more of these areas is a plus: fabric, memory controller, security, caches, coherence, MMU, high speed interfaces/protocols
  • Familiarity with high performance and low power design techniques
  • Some hands-on experience in design verification and/or physical design

Roles and Responsibilities

  • Work with chip architect to understand architecture concept and high level requirements
  • Convert chip spec to RTL using internal and external IPs
  • Plan and deliver RTL for continuous integration testing
  • Support the verification team to devise appropriate test plans and verification strategy
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