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DV - SOC - Power Management Verification

Bengaluru, India — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as an SOC Design Verification Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a SOC DV Engineer with a focus on Power Management verification, you will work to understand the internal requirements and complexities of our SOC system and architect the required verification strategy.  You will help set up methodologies, come up with test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.

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Minimum qualifications

  • BA/BS degree in Electrical Engineering with 7+ years of practical experience
  • Strong fundamentals in digital ASIC verification
  • Experience in verification of clock, reset , power management units and power gating controllers.
  • Experience in UPF based Power verification
  • Good understanding of master/slave components for PMIC interfaces
  • Experience in power and performance telemetry
  • Experience in TDP (thermal design power) capping and control verification
  • Strong programmable language experience is required (one or more of Verilog, SystemVerilog, Perl, Python, Tcl Scripts, Makefile and/or C++)

Preferred qualifications

  • MS degree in Electrical Engineering; 7+ years of practical experience
  • Experience in setting up Power estimation flows using static/dynamic tools
  • Expertise in the verification of ARM based CPUSS verification [ SMMU , GIC , Fabric etc ]
  • Strong understanding of AMBA bus protocols
  • A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
  • Extensive knowledge in multiple testbench structures
  • Knowledge of FPGA and emulation platforms
  • Proficiency in UVM, C/C++
  • Experience w/ PSS or higher level test construction languages
  • Knowledge of assertion-based formal verification

Roles and Responsibilities

  • Define entire verification architecture for all system level power management flows
  • Deep dive into microarchitecture of all agents and subsystems involved with power management flows
  • Define verification architecture, develop test plans and build verification environment
  • Work with design team to understand design intent and bring up verification plans and schedules
  • Verify Subsystems and Full SoC using advanced verification methodologies
  • Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard
  • Debug test cases and report verification result to achieve expected code/functional coverage goal
  • Assist in emulation, FPGA, prototyping efforts
  • Assist in silicon bring-up, debug and characterization
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