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SoC Power Management Micro-architect/RTL Engineer

Austin, TX — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a design engineer responsible for power management of a complex SOC. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Power Management design engineer, you will work with chip architects to develop  the power management micro-architecture as well as deliver the RTL design for the relevant blocks. Your contributions in this high-visibility role will enable an efficient and high performance compute SoC.

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Minimum qualifications

  • BA/BS degree in Electrical Engineering with 5 years of practical experience designing power management controllers in successfully shipped, high volume products
  • Strong fundamentals in digital ASIC design and power of CMOS circuits

Preferred qualifications

  • MS degree in Electrical Engineering; 10 years of practical experience
  • Experience in design of one or more power management units (PMU).
  • Experience in design of clock, reset and power gating controllers.
  • Experience in designing sequencers for power management.
  • Experience in design of resource management of one or more SoC components like DRAM, PCIe or other IO interfaces.
  • Experience in design of master/slave components for PMIC interfaces
  • Familiarity with high performance and low power design techniques
  • Experience in power and performance telemetry
  • Experience in TDP (thermal design power) capping and control

Role and Responsibilities

  • Work with SoC architects to understand architecture concept and high level power management requirements
  • Define the micro-architecture of the control system that drives power state control and transitions (FSM and/or micro controller based)
  • Implement the sequencers and state machines responsible for the power state management of the SoC components.
  • Implement the power management protocols between the various SoC blocks.
  • Support validation of the various control loops/sequences.
  • Must have good communication skills and able to work in dynamic environment with top level engineers and technologists
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