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DV - Emulation & FPGA

Santa Clara, CA — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as an Emulation Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As an Emulation Design Engineer, you will work with microarchitecture and RTL design team to implement the designs, develop, modify, and/or test hardware needed at the chip-level or block-level. 

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Minimum qualifications

  • FPGA and emulator flows and methodologies
  • Verilog and SystemVerilog
  • Emulator platforms (Cadence Palladium), platform bringup, digital design, verification, debugging, and waveform viewers
  • Hardware emulators, such as Palladium, ZeBu, Veloce, or FPGA systems based on Xilinx or Altera FPGAs
  • Vivado, Incisive/VCS, IXCOM, Design Compiler, Synplify, Verdi, or SimVision
  • Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
  • Debugging system-level software 
  • Programming skills in C and C++ 
  • Scripting in Python, Tcl, or Perl

Preferred qualifications

  • MS degree in Electrical Engineering or equivalent; 10 years of practical experience
  • Knowledge of CPU microarchitectures
  • Experience in deep submicron process technology nodes is strongly preferred 
  • Knowledge of library cells and optimizations from ARM, TSMC, and other high performance library vendors
  • Solid understanding industry standard tools for FPGA and Emulation platforms

Roles and Responsibilities

  • Drive block and full-chip level emulation (FPGA & emulator), and be responsible for QoR (timing, capacity) and debug
  • Work with CPU microarchitecture and design team to understand specifications and design tradeoffs in pipeline and structure sizing to achieve best-in-class performance and power over 3GHz
  • Synthesize the Verilog RTL and create models and compile them to Cadence Palladium and Protium platforms
  • Develop all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis
  • Work on third-party IP integration and system-level debugging
  • Block and system level RTL simulation & design verification
  • Support chip bring up and post silicon debug
  • Work with architects to select targeted kernels for benchmarking functional performance and timing on simulation and emulation platforms, and correlate timing between the two platforms
  • Perform feasibility studies to validate performance, functionality, and timing on emulation and simulation platforms
  • Debug functional and timing models
  • Validate the designs for functional and electrical robustness
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