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IC Packaging Layout Engineer

Santa Clara, CA — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a IC Packaging Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. 

As an IC Packaging Layout Engineer,  you are responsible for advanced IC packaging design, from design concept to product tape out.

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Minimum qualifications

  • Bachelor’s degree in Electrical Engineering or related fields and 5+ years of related professional experience.  Master’s degree in Electrical Engineering or related fields with 3+ years of experience.
  • Proficient in Cadence APD & SiP
  • Must have hand-on experience in package design, design for manufacturing review.
  • Familiar with flip chip package substrate

Preferred qualifications

  • Knowledge of high-speed IO interfaces including DDR/PCIE/Ethernet.
  • Proven design experience on 2.5D silicon interposer, from design concept, feasibility layout to final DRC / LVS checking.
  • Familiar with 2.5D heterogeneous integration package material and process.
  • Good knowledge and experience on layout review tools such as CAM350/Valor or Calibre.

Role and Responsibilities

  • Work with cross-functional teams to define and develop design flow, optimizing silicon floor plan, bump and package pinout.
  • Setup design rule and implement in-house packaging layout to meet all requirements for products.
  • Optimize package design on signal/power integrity, collaborate with the SI/PI team on package model extraction and analysis.
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