Skip to main content

Silicon Engineering

Home > Careers > Available Positions

SOC DRAM System Architect

Santa Clara, CA — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a SOC DDRAM System Architect. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a SOC DRAM System Architect, you will define the DRAM controller and PHY architecture for the main memory. In addition, you will work with SoC architects to influence chip architecture to maximize memory performance and power efficiency.

Apply for this job

Minimum qualifications

  • BS/MS/PhD in Computer Science/Computer Engineering/Electrical Engineer with more than 5 years experience in memory controller architecture, microarchitecture or RTL design.
  • Strong understanding of DDR4 and DDR5 DRAM technologies including 3DS
  • Strong understanding of various DIMM solutions (RDIMM, LRDIMM) 
  • Expertise in memory controller modeling in C/C++/SystemC
  • Proficient in scripting languages such as Perl or Python
  • Ability to independently identify, troubleshoot and solve problems

Preferred qualifications

  • MS degree in Electrical Engineering; 10 years of practical experience
  • Experience with productizing DRAM/DIMM solutions for DDR3, DDR4 or similar technologies 
  • Strong understanding of training, calibration and tuning of DRAM interface for stability, performance and power optimization
  • Expertise with enterprise level RAS solutions for DRAM controllers
  • Familiarity with high performance and low power design techniques
  • Experience with the management of various traffic classes

Role and Responsibilities

  • Define DRAM controller and PHY architecture and microarchitecture to maximize performance and power efficiency
  • Define microarchitecture of the controller including clocking and low power architecture.
  • Develop C/C++ models with varying levels of abstraction
  • Assess PPA trade-offs for various optimization proposals
  • Collaborate with performance architects to optimize system as well as the simulators
  • Simulate, analyze and present data to drive decisions
  • Verify the performance model correlates with the RTL, which may involve writing verification plans, writing directed tests, and writing checkers
Apply for this job

To all recruitment agencies:

NUVIA Inc does not accept agency resumes. Please do not forward resumes to our jobs alias, NUVIA Inc employees or any other company location. NUVIA Inc is not responsible for any fees related to unsolicited resumes.