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CAD - PDV Engineer

Santa Clara, CA — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a CAD Engineer. Our mission is to re-imagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a CAD Engineer focusing on physical design verification, you will work with design, and verification leads to develop technology and methodology critical to the development of our products. You will be involved from conception to final creation and every step along the way.

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Minimum qualifications

  • BA/BS degree in EE, CE, or CS with 7+ years of practical experience
  • Strong fundamentals in physical verification : DRC, LVS, DFM, PERC, LFD, etc.
  • Experience with layout mask design techniques and concerns
  • Experience with SVRF language and verification runsets
  • Experience with writing scripts/flows using Python or Perl

Preferred qualifications

  • MS degree in EE, CE, or CS with 10+ years of practical experience
  • Strong experience driving industry standard PDV tools including debuggers, steppers
  • Experienced with PDV at large scale (100+ parallel compute, many TB memory etc)
  • Experience with waiver technologies using industry tools
  • Experience with analog layout rules and checks such as latch-up, ESD, antenna, for modern advanced process nodes (multi-patterning, coloring etc)
  • Experience with digital design flow physical verification challenges
  • Able to use SVRF or TVF to create polygons and structures to solve challenges such as via fill, clock signal caging, metal fill, etc.
  • Familiar with AMS design flow
  • Experienced with modern custom and digital hierarchical release flow with data management
  • Experience with post-layout extraction (LPE) both digital (LEF/DEF) and analog (gds)
  • Familiar with SKILL coding for automation
  • Excellent debug and communication skills

Roles and Responsibilities

  • Work with design and CAD leads to develop PDV methodology to enable tapeout
  • Create flows/scripts/utilities in support of PDV
  • Train and support design teams relating to PDV closure
  • Work with integration team to close final verification
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