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PCIe DV Engineer

Santa Clara, CA — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a PCIe Design Verification Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a PCIe Design Verification Engineer you will help set up methodologies, come up with test plans, and verify the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.

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Minimum qualifications

  • Strong SV/UVM Knowledge and Coding Skills
  • Deep knowledge of full stack PCIe Gen4/5 (TLP, DLL, LTSSM, MSI, PHY bringup, Device Enum, etc)
  • 12-15+ years experience

Preferred qualifications

  • MS degree in Electrical Engineering; 7 years of practical experience
  • A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
  • Extensive knowledge in multiple testbench structures
  • Knowledge of FPGA and emulation platforms
  • Proficiency in UVM
  • PCIe/CXL support and compliance
  • Knowledge of assertion-based formal verification
  • Domain knowledge in one or more of these areas: fabric, memory controller, encryption, caches, coherence, MMU, high speed interfaces/protocols
  • I/O Coherency knowledge is preferred

Roles and Responsibilities

  • Define verification architecture, develop test plans and build verification environment
  • Work with design team to understand design intent and bring up verification plans and schedules
  • Verify SoC using advanced verification methodologies
  • Build agents and checkers from scratch
  • PCIe Full stack knowledge, UVM/SV
  • Perform and write test plan from design architecture specs and/or protocol standard
  • Debug test cases and report verification result to achieve expected code/functional coverage goal
  • Assist in emulation, FPGA, prototyping efforts
  • Assist in silicon bring-up, debug and characterization
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