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DV (Design Verification) Lead-Embedded

Santa Clara, CA — Full-time

Join the most cutting-edge and well-funded hardware startup in Silicon Valley as the engineer responsible for verification of an embedded microprocessor system. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Design Verification lead, you will work with chip architects to validate the concepts of microprocessor and SoC micro-architecture. You will be ultimately responsible for subsystem design verification to ensure that it functions.

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Minimum qualifications

  • BA/BS degree in CS or EE with 10+ years of direct design verification experience
  • In-depth knowledge of SoC function, architecture, and micro-architecture
  • Experience in writing test plans, portable benches, transactors, and assembly
  • Experience with many different verification methodologies and tools such as simulators, coverage collection, gate level simulation, waveform viewers, and mixed signal verification
  • Able to develop and work independently

Preferred qualifications

  • MS/PhD degree in CS or EE with 12+ years of SoC verification experience
  • Deep knowledge in SoC verification function and architecture
  • Have lead a small team of verification engineers doing SoC verification
  • Advanced techniques such as formal, assertions, and silicon bringup a plus

Role and Responsibilities

  • Work with chip architects to understand concept and high level system requirements
  • Develop detailed test and coverage plans based on the architecture and micro-architecture
  • Develop verification methodology, ensuring scalable and portable environment
  • Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage
  • Develop verification plans and test benches for your area 
  • Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures
  • Track and report DV progress using a variety of metrics, including bugs and coverage
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